SH7018 Datasheet, PDF (218/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the SCI1.
Module data bus
Internal
data bus
RxD
TxD
SCK
RDR1
TDR1
SSR1
BRR1
SCR1
RSR1
TSR1
SMR1
Transmit/
receive control
Baud rate
generator
Parity
generation
Clock
Parity check
External clock
RSR1 : Receive shift register
RDR1 : Receive data register
TSR1 : Transmit shift register
TDR1 : Transmit data register
SCI1
SMR1 : Serial mode register
SCR1 : Serial control register
SSR1 : Serial status register
BRR1 : Bit rate register
Figure 12.1 SCI1 Block Diagram
φ
φ/4
φ/16
φ/64
TEI
TxI
RxI
ERI
12.1.3 Pin Configuration
Table 12.1 summarizes the SCI1 pins by channel.
Table 12.1 SCI1 Pins
Pin Name
Serial clock pin
Receive data pin
Transmit data pin
Abbreviation
SCK
RxD
TxD
Input/Output
Input/output
Input
Output
Function
SCI1 clock input/output
SCI1 receive data input
SCI1 transmit data output
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