SH7018 Datasheet, PDF (191/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

9.4 Interrupts
9.4.1 Interrupt Source
When interrupt request flag CMF is set to 1, and interrupt enable bit CMIE is also 1, the
corresponding interrupt request is output.
9.4.2 Timing of Compare Match Flag Setting
The CMF bit in the T2CSR register is set to 1 by the compare match signal generated when the
T2COR register and T2CNT counter values match. The compare match signal is generated in the
last state in which the match is true (when the value at which the T2CNT counter match occurred
is about to be updated). Therefore, after a match between the T2CNT counter and the T2COR
register, the compare match signal is not generated until the next T2CNT counter input clock
pulse. Figure 9.4 shows the timing of CMF bit setting.
CK
T2CNT input clock pulse
T2CNT
N
0
T2COR
N
Compare match signal
CMF
CMI
Figure 9.4 Timing of CMF Setting
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