SH7018 Datasheet, PDF (68/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

5.3 Address Errors
Address errors occur when instructions are fetched or data read or written, as shown in table 5.6.
Table 5.6 Bus Cycles and Address Errors
Bus Cycle
Type
Bus Cycle Description
Instruction fetch Instruction fetched from even address
Instruction fetched from odd address
Instruction fetched from other than on-chip peripheral
module space*
Instruction fetched from on-chip peripheral module
space*
Data read/write Word data accessed from even address
Word data accessed from odd address
Longword data accessed from other than a longword
boundary
Byte or word data accessed in on-chip peripheral
module space*
Longword data accessed in 16-bit on-chip peripheral
module space*
Longword data accessed in 8-bit on-chip peripheral
module space*
Note: * See section 7, Bus State Controller.
Address Errors
None (normal)
Address error occurs
None (normal)
Address error occurs
None (normal)
Address error occurs
Address error occurs
None (normal)
None (normal)
Address error occurs
5.3.1 Address Error Exception Processing
When an address error occurs, the bus cycle in which the address error occurred ends. When the
executing instruction then finishes, address error exception processing starts up. The CPU operates
as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
3. The exception service routine start address is fetched from the exception processing vector
table that corresponds to the address error that occurred and the program starts executing from
that address. The jump that occurs is not a delayed branch.
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