SH7018 Datasheet, PDF (111/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Section 8 Multifunction Timer Pulse Unit (MTU)
8.1 Overview
The SH7018 has an on-chip 16-bit multifunction timer pulse unit (MTU) with three channels of
16-bit timers.
8.1.1 Features
• Can process a maximum of six different pulse outputs and inputs.
• Has eight timer general registers (TGR), four for channel 0 and two each for channels 1 and 2,
that can be set to function independently as output compare registers or (except for TGR0B
and TGR0D of channel 0) as input capture registers. The channel 0 TGRC and TGRD registers
can be used as buffer registers.
• Can select six counter input clock sources for all channels
• All channels can be set for the following operating modes:
 Compare match waveform output: 0 output/1 output/toggle output selectable.
 Input capture function: Selectable rising edge, falling edge, or both rising and falling edge
detection.
 Counter clearing function: Counters can be cleared by a compare-match or input capture.
 Synchronizing mode: Two or more timer counters (TCNT) can be written to
simultaneously. Two or more timer counters can be simultaneously cleared by a compare-
match or input capture. Counter synchronization functions enable synchronized register
input/output.
 PWM mode: PWM output can be provided with any duty cycle. When combined with the
counter synchronizing function, enables up to four-phase* PWM output.
Note: * When channels 0 to 2 are set to PWM mode 1
• Channel 0 can be set for buffer operation
 Input capture register double buffer configuration possible
 Output compare register automatic re-write possible
• Cascade connection operation
 Can be operated as a 32-bit counter by using the channel 2 input clock for channel 1
overflow/underflow
• High speed access via internal 16-bit bus
• Eleven interrupt sources
 Channel 0 has two dual-function compare-match/input capture interrupts, two compare-
match interrupts, and one overflow interrupt, which can be requested independently.
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