SH7108 Datasheet, PDF (76/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
2.6 Processing States
2.6.1 State Transitions
The CPU has five processing states: reset, exception processing, bus release, program execution,
and power-down. Figure 2.4 shows the transitions between the states.
From nay state
when
=0
and
=1
From nay state when
= 0,
= 0,
and
=1
=0
=1
Power-on reset state
=0
Manual reset state
When an internal power-on
reset by WDT or internal
manual reset by
WDT occurs
Bus request
released
Bus release state
=1
= 1,
=1
Exception
processing state
Bus request
released ^Exception
processing
Bus request
source
released
occurs
Exception
processing
endws
Bus request
generated
Bus request
generated
Bus request
released
Program execution state
SSBY bit cleared
for SLEEP
instruction
SSBY bit set
for SLEEP
instruction
Reset state
Sleep mode
Software standby mode
Hardware standby mode
From any state when
= 0 and
=0
Power-down mode
Figure 2.4 Transitions between Processing States
Reset State: The CPU resets in the reset state. When the RES pin level goes low, the power-on
reset state is entered. When the RES pin is high and the MRES pin is low, the manual reset state is
entered. When the HSTBY pin is driven high and the RES pin level goes low, the power-on reset
state is entered.
Exception Processing State: The exception processing state is a transient state that occurs when
exception processing sources such as resets or interrupts alter the CPU’s processing state flow.
Rev.1.00 Sep. 18, 2008 Page 42 of 522
REJ09B0069-0100