SH7108 Datasheet, PDF (181/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
8.3.5 Timer Status Register (TSR)
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The
MTU has five TSR registers, one for each channel.
Initial
Bit Bit Name value
7
TCFD
1
6
—
1
5
TCFU
0
4
TCFV
0
R/W
R
R
R/(W)
R/(W)
Description
Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1, 2, 3, and 4.
In channel 0, bit 7 is reserved. It is always read as 1, and
should only be written with 1.
0: TCNT counts down
1: TCNT counts up
Reserved
This bit is always read as 1. The write value should
always be 1.
Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1 and 2 are set to phase
counting mode. Only 0 can be written, for flag clearing.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0, and the write value should always be 0.
[Setting condition]
• When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
• When 0 is written to TCFU after reading TCFU = 1
Overflow Flag
Status flag that indicates that TCNT overflow has
occurred. Only 0 can be written, for flag clearing.
[Setting condition]
• When the TCNT value overflows (changes from
H'FFFF to H'0000)
In channel 4, when TCNT-4 is underflowed (H'0001
→ H'0000) in complementary PWM mode.
[Clearing condition]
• When 0 is written to TCFV after reading TCFV = 1
Rev.1.00 Sep. 18, 2008 Page 147 of 522
REJ09B0069-0100