SH7108 Datasheet, PDF (423/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Initial
Bit Bit Name Value
11 to 9 ⎯
All 0
8
PIE
0
7, 6 ⎯
All 0
5
POE6M1 0
4
POE6M0 0
3
POE5M1 0
2
POE5M0 0
Section 13 Motor Management Timer (MMT)
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Port Interrupt Enable
Enables or disables an interrupt request when 1 is set in
any of bits POE4F to POE6F in ICSR2.
0: Interrupt request disabled
1: Interrupt request enabled
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W POE6 Mode 1 and 0
R/W
Select the input mode of the POE6 pin.
00: Request accepted at falling edge of POE6 input
01: POE6 input is sampled for low level 16 times every
Pφ/8 clock, and request is accepted when all
samples are low level
10: POE6 input is sampled for low level 16 times every
Pφ/16 clock, and request is accepted when all
samples are low level
11: POE6 input is sampled for low level 16 times every
Pφ/128 clock, and request is accepted when all
samples are low level
R/W POE5 Mode 1 and 0
R/W Select the input mode of the POE5 pin.
00: Request accepted at falling edge of POE5 input
01: POE5 input is sampled for low level 16 times every
Pφ/8 clock, and request is accepted when all
samples are low level
10: POE5 input is sampled for low level 16 times every
Pφ/16 clock, and request is accepted when all
samples are low level
11: POE5 input is sampled for low level 16 times every
Pφ/128 clock, and request is accepted when all
samples are low level
Rev.1.00 Sep. 18, 2008 Page 389 of 522
REJ09B0069-0100