SH7108 Datasheet, PDF (58/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Addressing
Mode
Indirect indexed
register
addressing
Instruction
Format
Effective Address Calculation
@(R0, Rn) The effective address is the sum of Rn and R0.
Rn
+
Rn + R0
Equation
Rn + R0
Indirect GBR
addressing with
displacement
R0
@(disp:8, The effective address is the sum of GBR value and Byte:
GBR)
an 8-bit displacement (disp). The value of disp is GBR + disp
zero-extended, and remains unchanged for a byte Word:
operation, is doubled for a word operation, and is _{GBR + disp ×}
quadrupled for a longword operation.
2
GBR
disp
(zero-extended)
Longword:
GBR + disp ×
+
GBR
4
+ disp × 1/2/4
×
Indirect indexed @(R0,
GBR addressing GBR)
1/2/4
The effective address is the sum of GBR value and GBR + R0
R0.
GBR
+
GBR + R0
Indirect PC
addressing with
displacement
R0
@(disp:8, The effective address is the sum of PC value and
PC)
an 8-bit displacement (disp). The value of disp is
zero-extended, and is doubled for a word
operation, and quadrupled for a longword
operation. For a longword operation, the lowest
two bits of the PC value are masked.
PC
Word:
PC + disp × 2
Longword:
PC &
H'FFFFFFFC
+ disp × 4
(for longword)
&
H'FFFFFFFC
+
disp
(zero-extended)
×
PC + disp × 2
or
PC & H'FFFFFFFC
+ disp × 4
2/4
Rev.1.00 Sep. 18, 2008 Page 24 of 522
REJ09B0069-0100