SH7108 Datasheet, PDF (239/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

TGRA_3
TCDR
TCNT_3
TCNT_4
TDDR
H'0000
Channel 1
Input capture A
TCNTS
TCNT_1
Section 8 Multifunction Timer Pulse Unit (MTU)
Synchronous counter clearing by channel 1 input capture A
Figure 8.49 Counter Clearing Synchronized with Another Channel
Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output: In
complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate
control register (TGCR). Figures 8.50 to 8.53 show examples of brushless DC motor drive
waveforms created using TGCR.
When output phase switching for a 3-phase brushless DC motor is performed by means of external
signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external
signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B,
and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the
output on/off state is switched automatically.
When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is
cleared to 0 or set to 1.
The drive waveforms are output from the complementary PWM mode 6-phase output pins. With
this 6-phase output, in the case of on output, it is possible to use complementary PWM mode
output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0,
level output is selected.
Rev.1.00 Sep. 18, 2008 Page 205 of 522
REJ09B0069-0100