SH7108 Datasheet, PDF (117/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Interrupt Controller (INTC)
IRQnS _ISR.IRQnF
IRQnES
IRQ pins
Level
detection
Edge
detection
SQ
CPU interrupt
request
RESIRQn
R
(Acceptance of IRQn interrupt/Writing 0 after reading IRQnF = 1)
Figure 6.2 Control of IRQ3 to IRQ0 Interrupts
6.4.2 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral
modules.
As a different interrupt vector is assigned to each interrupt source, the exception service routine
does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be
assigned to individual on-chip peripheral modules by setting interrupt priority registers A, D to K
(IPRA, IPRD to IPRK). On-chip peripheral module interrupt exception processing sets the
interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-
chip peripheral module interrupt that was accepted.
Rev.1.00 Sep. 18, 2008 Page 83 of 522
REJ09B0069-0100