SH7108 Datasheet, PDF (399/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Motor Management Timer (MMT)
13.3.1 Timer Mode Register (MMT_TMDR)
MMT_TMDR sets the operating mode and selects the PWM output level. (In this section, the
name of this register is abbreviated to TMDR hereafter.)
Initial
Bit Bit Name Value R/W Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
CKS2
0
5
CKS1
0
4
CKS0
0
R/W Clock Select 2 to 0
R/W Select the clock input to MMT.
R/W 000: Pφ
001: Pφ/4
010: Pφ/16
011: Pφ/64
100: Pφ/256
101: Pφ/1024
11x: Setting prohibited
[Legend] x: Don’t care.
3
OLSN
0
R/W Output Level Select N
Selects the negative phase output level in the
operating modes.
0: Active level is low
1: Active level is high
2
OLSP
0
R/W Output Level Select P
Selects the positive phase output level in the operating
modes.
0: Active level is low
1: Active level is high
1
MD1
0
0
MD0
0
R/W Mode 3 to 0
R/W Set the timer operating mode.
00: Operation halted
01: Operating mode 1 (Transfer at TCNT = TPDR)
10: Operating mode 2 (Transfer at TCNT = TDDR × 2)
11: Operating mode 3 (Transfer at TCNT = TPDR or
TCNT = TDDR × 2)
Rev.1.00 Sep. 18, 2008 Page 365 of 522
REJ09B0069-0100