SH7108 Datasheet, PDF (407/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Motor Management Timer (MMT)
2
TGRUU
+
TGRVU
TGRWU ^{(TBR + 2Td)}
Compared during
up-count
TDDR
(Td)
TBRU
TBRV
TBRW
(TBR)
TPBR
(1/2 period)
TDDR
(Td)
+
+
2
TGRU
TGRV
TGRW
(TBR + Td)
TCNT
TGRUD
TGRVD
TGRWD ^(TBR)
Constantly
compared
Compared during
down-count
(1/2 period + 2Td)
TPDR
TCNT
(2Td)
Compared during Up-count compare
up-count
match down-count
Compared during Down-count compare
down-count
match up-count
TDDR (Td)
TDCNT
Up-count compare match halt
Figure 13.4 Examples of Counter and Register Operations
(3) Initial Settings
In the operating modes, there are five registers that require initialization.
Make the following register settings before setting the operating mode with bits MD1 and MD0 in
the timer mode register (TMDR).
Set the timer period buffer register (TPBR) to 1/2 the PWM carrier period, set dead time Td in the
timer dead time data register (TDDR) (when outputting an ideal waveform, Td = H'0000), and set
{TPBR value + 2Td} in the timer period data register (TPDR).
Set {PWM duty initial value – Td} in the free write operation addresses for TBRU to TBRW.
Rev.1.00 Sep. 18, 2008 Page 373 of 522
REJ09B0069-0100