SH7108 Datasheet, PDF (265/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
Pφ
TCNT input
clock
TCNT
Counter clear
signal
TGF
H'FFFF
H'0000
TCFV
Disabled
Figure 8.82 Contention between Overflow and Counter Clearing
8.7.17 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 8.83 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T1
T2
Pφ
Address
TCNT address
Write signal
TCNT
H'FFFF
TCNT write data
M
TCFV flag
Figure 8.83 Contention between TCNT Write and Overflow
Rev.1.00 Sep. 18, 2008 Page 231 of 522
REJ09B0069-0100