SH7108 Datasheet, PDF (425/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Motor Management Timer (MMT)
P
Sampling clock
input
PUOA
All low-level samples
At least one high-level
sample
8, 16, or
128 clocks
[1]
[2]
[1]
[2]
High-impedance state
[3]
[16] Flag set (POE accepted)
[13] Flag not set
Note: The other MMT output pins also enter the high-impedance state at the same timing.
Figure 13.18 Low Level Detection Operation
(2) Exiting High-Impedance State
The MMT output pins that have entered the high-impedance state by the input level detection are
released from this state by restoring them to their initial states by means of a power-on reset, or by
clearing all the POE flags in ICSR2 (POE4F to POE6F: bits 12 to 14).
13.8.5 Usage Note
To set the POE pin as a level-detective pin, a high level signal must be firstly input to the POE
pin.
Rev.1.00 Sep. 18, 2008 Page 391 of 522
REJ09B0069-0100