SH7108 Datasheet, PDF (253/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

TCLKA
(TCLKC)
TCLKB
(TCLKD)
Phase
Phase
differ-
differ-
Overlap ence Overlap ence
Section 8 Multifunction Timer Pulse Unit (MTU)
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 8.69 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
8.7.3 Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
f = ^Pφ
(N + 1)
Where
f : Counter frequency
Pφ : Peripheral clock operating frequency
N : TGR set value
8.7.4 Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed.
Figure 8.70 shows the timing in this case.
Rev.1.00 Sep. 18, 2008 Page 219 of 522
REJ09B0069-0100