SH7108 Datasheet, PDF (419/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Motor Management Timer (MMT)
TGRU
Td
PreviousTGRU
PreviousTGRU
Td
TGRU
2Td
2Td
Count-up
Count down
Figure 13.16 Writing into Timer General Registers (When One Cycle is Not Output)
(4) Writing Operation into Timer Period Data Register (TPDR) and Timer Dead Time Data
Register (TDDR) When MMT is Operating
• Do not revise TPDR register when MMT is operating. Always use a buffer-write operation
through TPBR register.
• Do not revise TDDR register once an operation of MMT is invoked. When TDDR is revised, a
wave may not be output for as much as 1 cycle (full count period of 16 bits in TDCNT),
because a value cannot be written into TDCNT, which is compared to a value set in TDDR.
(5) Notes on Halting TCNT Counter Operation
If TCNT counter operation is halted, a PCM waveform may be output with dead time (non-overlap
time) shorter than the value set in the timer dead time register (MMT_TDDR) or no dead time at
all (value of 0). To prevent this, use one of the following methods.
(a) Set the CST bit in the timer control register (TCNR) to 1 and do not clear it to 0 after MMT
counter operation starts. If the CST bit is cleared to 0, do not set it to 1 again.
(b) When setting, clearing, and then resetting the CST bit, use the following procedure for clearing
and then resetting.
(1) Use the pin function controller (PFC) to set the PWM output pin as a general input port.
(2) Set the free operation addresses for all the buffer registers (TBRU, TBRV, and TBRW) to
H'0000.
(3) After the specified dead time duration has elapsed, set TCNR to H'00 and clear the CST bit
to 0.
(4) Once again, set the CST bit to 1.
Rev.1.00 Sep. 18, 2008 Page 385 of 522
REJ09B0069-0100