SH7108 Datasheet, PDF (418/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Motor Management Timer (MMT)
(2) Contention between Compare Register Write and Compare Match
If a compare match occurs in the T2 state of a compare register (TGR or TPDR) write cycle, the
compare register write is not performed, and data is transferred from the buffer register (TBRU,
TBRV, TBRW, or TPBR) to the compare register by a buffer operation.
Figure 13.15 shows the timing in this case.
P
Address
Compare register
write cycle
T1 T2
Compare register
address
Write signal
Compare match
signal
Interrupt request
signal
Buffer register
N
Compare register
N
Figure 13.15 Contention between Compare Register Write and Compare Match
(3) Pay Attention to the Notices Below, When a Value is Written into the Timer General
Register U (TGRU), Timer General Register V (TGRV), Timer General Register W
(TGRW), and in Case of Written into Free Operation Address (*)
• In case of counting up: Do not write a value {Previous value of TGRU + Td} into TGRU.
• In case of counting down: Do not write a value {Previous value of TGRU - Td} into TGRU.
In the same manner to TGRV and TGRW. When a value {Previous value of TGRU + Td} is
written (in case of counting down {Previous value of TGRU - Td}), the output of PUOA/PUOB,
PVOA/PVOB, PWOA/PWOB (corresponding to U, V, W phase) may not be output for 1 cycle.
Figure 15.17 shows the error case. When writing into the buffer operation address, these notes are
not relevant.
Note: * When addresses, H'FFFF8A1C, H'FFFF8A2C, H'FFFF8A3C are used as register
address for TBRU, TBRV, TBRW, respectively.
Rev.1.00 Sep. 18, 2008 Page 384 of 522
REJ09B0069-0100