SH7108 Datasheet, PDF (256/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
8.7.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation differs depending on channel 0 and channels 3 and 4: data on channel 0 is
that after write, and on channels 3 and 4, before write.
Figures 8.73 and 8.74 show the timing in this case.
Pφ
Address
Write signal
Compare
match signal
Compare
match buffer
signal
Buffer register
TGR write cycle
T1 T2
Buffer register
address
Buffer register write data
N
M
TGR
M
Figure 8.73 Contention between Buffer Register Write and Compare Match (Channel 0)
Rev.1.00 Sep. 18, 2008 Page 222 of 522
REJ09B0069-0100