SH7108 Datasheet, PDF (443/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Pin Function Controller (PFC)
14.1 Register Descriptions
The PFC has the following registers. For details on the addresses of the registers and their states
during each process, refer to section 19, List of Registers.
• Port A I/O register L (PAIORL)
• Port A control register L3 (PACRL3)
• Port A control register L2 (PACRL2)
• Port A control register L1 (PACRL1)
• Port B I/O register (PBIOR)
• Port B control register 1 (PBCR1)
• Port B control register 2 (PBCR2)
• Port D I/O register L (PDIORL)
• Port D control register L1 (PDCRL1)
• Port D control register L2 (PDCRL2)
• Port E I/O register H (PEIORH)
• Port E I/O register L (PEIORL)
• Port E control register H (PECRH)
• Port E control register L1 (PECRL1)
• Port E control register L2 (PECRL2)
14.1.1 Port A I/O Register L (PAIORL)
PAIORL is a 16-bit readable/writable register that sets the pins on port A as inputs or outputs. Bits
PA15IOR to PA0IOR correspond to pins PA15 to PA0 (names of multiplexed pins are here given
as port names and pin numbers alone). PAIORL is enabled when the port A pins are functioning as
general-purpose inputs/outputs (PA15 to PA0), SCK2 and SCK3 pins are functioning as
inputs/outputs of the SCI, and PCIO pin is functioning as an input/output of the MMT. In other
states, PAIORL is disabled.
A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an
input pin if the bit is cleared to 0.
The initial value of PAIORL is H'0000.
14.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1)
PACRL3 to PACRL1 are 16-bit readable/writable registers that select the functions of the
multiplexed pins on port A.
Rev.1.00 Sep. 18, 2008 Page 409 of 522
REJ09B0069-0100