SH7108 Datasheet, PDF (49/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Section 2 CPU
2.1 Features
• General-register architecture
⎯ Sixteen 32-bit general registers
• Sixty-two basic instructions
• Eleven addressing modes
⎯ Register direct [Rn]
⎯ Register indirect [@Rn]
⎯ Register indirect with post-increment [@Rn+]
⎯ Register indirect with pre-decrement [@-Rn]
⎯ Register indirect with displacement [@disp:4,Rn]
⎯ Register indirect with index [@R0, Rn]
⎯ GBR indirect with displacement [@disp:8,GBR]
⎯ GBR indirect with index [@R0,GBR]
⎯ Program-counter relative with displacement [@disp:8,PC]
⎯ Program-counter relative [disp:8/disp:12/Rn]
⎯ Immediate [#imm:8]
2.2 Register Configuration
The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four
32-bit system registers.
CPUS200A_010020030200
Rev.1.00 Sep. 18, 2008 Page 15 of 522
REJ09B0069-0100