SH7108 Datasheet, PDF (257/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
TGR write cycle
T1
T2
Pφ
Address
Buffer register
address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
Buffer register write data
N
M
TGR
N
Figure 8.74 Contention between Buffer Register Write and Compare Match
(Channels 3 and 4)
8.7.8 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 8.75 shows the timing in this case.
Rev.1.00 Sep. 18, 2008 Page 223 of 522
REJ09B0069-0100