SH7108 Datasheet, PDF (123/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Interrupt Controller (INTC)
6.6.2 Stack after Interrupt Exception Processing
Figure 6.4 shows the stack after interrupt exception processing.
Address
4n–8
4n–4
4n
PC^*1
SR
32 bits
32 bits
SP^*2
Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executing
instruction
2. Always make sure that SP is a multiple of 4.
Figure 6.4 Stack after Interrupt Exception Processing
Rev.1.00 Sep. 18, 2008 Page 89 of 522
REJ09B0069-0100