SH7108 Datasheet, PDF (222/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
Example of Complementary PWM Mode Setting Procedure: An example of the
complementary PWM mode setting procedure is shown in figure 8.33.
1. Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter
(TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4
are stopped.
2. Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2 to TPSC0 and
bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2 to CCLR0 to set
synchronous clearing only when restarting by a synchronous clear from another channel during
complementary PWM mode operation.
3. When performing brushless DC motor control, set bit BDC in the timer gate control register
(TGCR) and set the feedback signal input source and output chopping or gate signal direct
output.
4. Set the dead time in TCNT_3. Set TCNT_4 to H'0000.
5. Set only when restarting by a synchronous clear from another channel during complementary
PWM mode operation. In this case, synchronize the channel generating the synchronous clear
with channels 3 and 4 using the timer synchro register (TSYR).
6. Set the output PWM duty cycle in the duty cycle registers (TGRB_3, TGRA_4, TGRB_4) and
buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each
corresponding TGR.
7. Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle
data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus
the dead time in TGRA_3 and TGRC_3.
8. Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE
in the timer output control register (TOCR), and set the PWM output level with bits OLSP and
OLSN.
9. Select complementary PWM mode in timer mode register 3 (TMDR_3). Pins TIOC3A,
TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D function as output pins*. Do
not set in TMDR_4.
10. Set enabling/disabling of PWM waveform output pin output in the timer output master enable
register (TOER).
11. Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation.
Note: * PFC registers should be specified before this procedure.
Rev.1.00 Sep. 18, 2008 Page 188 of 522
REJ09B0069-0100