SH7108 Datasheet, PDF (261/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
TCNT write cycle
T1 T2
Pφ
Address
TCNT_2 address
Write signal
TCNT_2
TGR2A_2 to
TGR2B_2
Ch2 compare-
match signal A/B
TCNT_1 input
clock
TCNT_1
H'FFFE
H'FFFF
N
TCNT_2 write data
H'FFFF
N+1
Disabled
M
TGRA_1
Ch1 compare-
match signal A
TGRB_1
Ch1 input capture
signal B
TCNT_0
M
N
M
P
TGRA_0 to
TGRD_0
Ch0 input capture
signal A to D
Q
P
Figure 8.78 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection
8.7.12 Counter Value during Complementary PWM Mode Stop
When counting operation is stopped with TCNT_3 and TCNT_4 in complementary PWM mode,
TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is set to H'0000.
When restarting complementary PWM mode, counting begins automatically from the initialized
state. This explanatory diagram is shown in figure 8.79.
Rev.1.00 Sep. 18, 2008 Page 227 of 522
REJ09B0069-0100