SH7108 Datasheet, PDF (263/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer
register for TRGA_4.
The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are
operating as buffer registers.
Figure 8.80 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with
TMDR_3’s BFA and BFB bits set to 1, and TMDR_4’s BFA and BFB bits set to 0.
TGRA_3
TGRC_3
TCNT3
Point a
TGRB_3, TGRA_4,
TGRB_4
TGRD_3, TGRC_4, ^{Point b}
TGRD_4
H'0000
Buffer transfer with
compare match A3
TGRA_3,
TGRC_3
TGRB_3, TGRD_3,
TGRA_4, TGRC_4,
TGRB_4, TGRD_4
TIOC3A
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
TGFC
TGFD
Not set
Not set
Figure 8.80 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode
8.7.15 Overflow Flags in Reset Sync PWM Mode
When set to reset sync PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of
TSTR is set to 1. At this point, TCNT_4’s count clock source and count edge obey the TCR_3
setting.
In reset sync PWM mode, with cycle register TGRA_3’s set value at H'FFFF, when specifying
TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF,
Rev.1.00 Sep. 18, 2008 Page 229 of 522
REJ09B0069-0100