SH7108 Datasheet, PDF (306/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Watchdog Timer
ITI (interrupt
request signal)
WDTOVF
Internal reset
signal*
Interrupt
control
Overflow
Clock
Reset
control
Clock
select
φ/2
φ/64
φ/128
φ/256
φ/512
φ/1024
φ/4096
φ/8192
Internal clock
sources
RSTCSR
TCNT
TSCR
Module bus
Bus
interface
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
RSTCSR: Reset control/status register
WDT
Note: * The internal reset signal can be generated by making a register setting.
Power-on reset or manual reset can be selected.
Figure 9.1 Block Diagram of WDT
9.2 Input/Output Pin
Table 9.1 shows the pin configuration of the watchdog timer.
Table 9.1 Pin Configuration
Pin
Abbreviation I/O
Function
Watchdog timer overflow WDTOVF
Output
Outputs the counter overflow signal in
watchdog timer mode
Note: The WDTOVF pin should not be pulled down. However, if it is necessary to pull this pin
down, a resistance of 1 MΩ or higher should be used.
9.3 Register Descriptions
The WDT has the following three registers. For details, refer to section 19, List of Registers. To
prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method
different from normal registers. For details, refer to section 9.6.1, Notes on Register Access.
Rev.1.00 Sep. 18, 2008 Page 272 of 522
REJ09B0069-0100