SH7108 Datasheet, PDF (166/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
Table 8.13 TIORL_0 (Channel 0)
Description
Bit 3 Bit 2 Bit 1 Bit 0 TGRC_0
IOC3 IOC2 IOC1 IOC0 Function
TIOC0C Pin Function
0
0
0
0
Output
Output hold*¹
1
compare
Initial output is 0
register*
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output value retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input
Input capture at rising edge
1
capture
Input capture at falling edge
register*
1
x
Input capture at both edges
1
x
x
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Legend: x: Don’t care
Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.1.00 Sep. 18, 2008 Page 132 of 522
REJ09B0069-0100