SH7108 Datasheet, PDF (490/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 18 Power-Down Modes
• MSTCR2
Bit
Bit Name
15
⎯
Initial
Value
1
R/W
R
14
MSTP14 1
R/W
13
MSTP13 1
R/W
12
MSTP12 1
R/W
11 to 8 ⎯
All 0
R
7
⎯
1
R
6
MSTP6 1
R/W
5
MSTP5 1
R/W
4
MSTP4 1
R/W
3 to 0 ⎯
All 0
R
Description
Reserved
This bit is always read as 1. The write value should
always be 1.
Motor management timer (MMT)
Multifunction timer pulse unit (MTU)
Compare match timer (CMT)
Reserved
These bits are always read as 0. The write value
should always be 0
Reserved
This bit is always read as 1. The write value should
always be 1.
A/D converter (A/D2)
A/D converter (A/D1)
A/D converter (A/D0)
Reserved
These bits are always read as 0. The write value
should always be 0.
18.3 Operation
18.3.1 Sleep Mode
(1) Transition to Sleep Mode
If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the CPU enters
sleep mode. In sleep mode, CPU operation stops, however the contents of the CPU's internal
registers are retained. Peripheral functions except the CPU do not stop.
(2) Clearing Sleep Mode
Sleep mode is cleared by the conditions below.
• Clearing by a power-on reset
When the RES pin is driven low, the CPU enters the reset state. When the RES pin is driven
high after the elapse of the specified reset input period, the CPU starts the reset exception
handling.
Rev.1.00 Sep. 18, 2008 Page 456 of 522
REJ09B0069-0100