SH7108 Datasheet, PDF (348/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 Serial Communication Interface (SCI)
10.5.1 Multiprocessor Serial Data Transmission
Figure 10.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Initialization
[1]
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Yes
No
[3]
Read TEND flag in SSR
TEND = 1
Yes
Break output?
Yes
Clear DR to 0
No
No
[4]
Clear TE bit in SCR to 0;
select the TxD pin
as an output port with the PFC
[1] SCI initialization:
Set the TxD pin using the PFC.
After the TE bit is set to 1, 1 is
output for one frame, and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, first clear the port
data register (DR) to 0, then
clear the TE bit to 0 in SCR and
use the PFC to select the TxD
pin as an output port.
<End>
Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart
Rev.1.00 Sep. 18, 2008 Page 314 of 522
REJ09B0069-0100