SH7108 Datasheet, PDF (142/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Bus State Controller (BSC)
When the wait is specified by software using WCR1, the wait input WAIT signal from outside is
sampled. Figure 7.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when the TW state shifts to the T2 state. When using external
waits, use a WCR1 setting of 1 state or more in case of extending CS assertion, and 2 states or
more otherwise.
CK
Address
T1
TW
TW
TWo
T2
Read
Data
Write
Data
Figure 7.5 Wait State Timing of External Space Access
(Two Software Wait States + WAIT Signal Wait State)
Rev.1.00 Sep. 18, 2008 Page 108 of 522
REJ09B0069-0100