SH7108 Datasheet, PDF (108/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Interrupt Controller (INTC)
Figure 6.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
MTU
CMT
MMT
A/D
SCI
WDT
I/O
Input
control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR1
ICR2
ISR
IPR
IPRA, IPRD to IPRK
Module bus
Bus
interface
INTC
Legend:
MTU: Multifunction timer pulse unit
CMT: Compare match timer
MMT: Motor management timer
A/D: A/D converter
SCI: Serial communication interface
WDT:
I/O:
ICR1, ICR2:
ISR:
IPRA, IPRD to IPRK:
SR:
Watchdog timer
I/O port (Port output controller)
Interrupt control register
IRQ status register
Interrupt priority level setting registers A, D to K
Status register
Figure 6.1 INTC Block Diagram
Rev.1.00 Sep. 18, 2008 Page 74 of 522
REJ09B0069-0100