SH7108 Datasheet, PDF (122/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Interrupt Controller (INTC)
Program
execution state
Interrupt?
No
Yes
No
NMI?
Yes
= low ^*1
Save SR to stack
Save PC to stack
Copy accept-interrupt
level to I3 to I0
= high
*2
Read exception
vector table
Branch to exception
service routine
Level 15
No
interrupt?
Yes
Level 14
No
Yes
I3 to I0 ≤
interrupt?
level 14?
Yes
Level 1 ^No
No
Yes
I3 to I0 ≤
interrupt?
level 13?
Yes
No
Yes
I3 to I0 =
level 0?
No
Notes: I3 to I0 are Interrupt mask bits of status register (SR) in the CPU.
1.
is the same signal as interrupt request signal to the CPU (see figure 6.1).
Therefore,
is output when the request priority level is higher than the level in bits I3 to I0 of SR.
2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when
the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack).
However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted
and has output an interrupt request to the CPU, the
pin holds low level.
Figure 6.3 Interrupt Sequence Flowchart
Rev.1.00 Sep. 18, 2008 Page 88 of 522
REJ09B0069-0100