SH7108 Datasheet, PDF (38/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

: Peripheral address bus (12 bits)
: Peripheral data bus (16 bits)
: Internal address bus (32 bits)
: Internal upper data bus (16 bits)
: Internal lower data bus (16 bits)
Figure 1.2 Internal Block Diagram of SH7109/SH7107/SH7105
Rev.1.00 Sep. 18, 2008 Page 4 of 522
REJ09B0069-0100
PD8
PD7/D7
PD6/D6
PD5/D5
PD4/D4
PD3/D3
PD2/D2/SCK2
PD1/D1/TxD2
PD0/D0/RxD2
Motor management
timer (x 1 channel)
AVss
AVss
AVcc
AVcc
converter timer
Compare match timer
(x 2 channels)
Vss
Watchdog
A/D
Vss
Vss
Multifunction timer
pulse unit
Serial communication
interface (x 2 channels)
Vss
Vss
Vcc
Vcc
Vcc
Bus state controller
Interrupt controller
Vcc
Vcc
VCL
CPU
VCL
PLLVss
L
L
PLLCAP
P
PLLVCL
XTAL
EXTAL
RAM
8 kbytes/4 kbytes
Masked ROM
256 kbytes/
128 kbytes/64 kbytes
NMI
MD0
MD1
MD2
MD3
HSTBY
WDTOVF
RES
Section 1 Overview