SH7108 Datasheet, PDF (494/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 18 Power-Down Modes
Oscillator
CK
NMI pin
NMIE bit
SSBY bit
LSI state ^Program
NMI
exception
Exception
execution state _handling service routine
Software
standby mode
Oscillation WDT NMI exception
start time setting time handling
Oscillation stabilization
time
Figure 18.2 NMI Timing in Software Standby Mode
18.3.3 Hardware Standby Mode
(1) Transition to Hardware Standby Mode
When the HSTBY pin is driven low, a transition is made to hardware standby mode from any
mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power consumption. As long as the specified voltage is supplied, on-chip
RAM data is retained.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the HSTBY pin low. Do not change the state of the mode pins (MD3 to MD0) while the
CPU is in hardware standby mode.
Rev.1.00 Sep. 18, 2008 Page 460 of 522
REJ09B0069-0100