SH7108 Datasheet, PDF (386/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 12 Compare Match Timer (CMT)
12.2 Register Descriptions
The CMT has the following registers. For details on register addresses and register states during
each processing, refer to section 19, List of Registers.
• Compare match timer start register (CMSTR)
• Compare match timer control/status register_0 (CMCSR_0)
• Compare match timer counter_0 (CMCNT_0)
• Compare match timer constant register_0 (CMCOR_0)
• Compare match timer control/status register_1 (CMCSR_1)
• Compare match timer counter_1 (CMCNT_1)
• Compare match timer constant register_1 (CMCOR_1)
12.2.1 Compare Match Timer Start Register (CMSTR)
CMSTR is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1
counters (CMCNT).
Bit Bit Name
15 to 2 ⎯
Initial
Value
All 0
1
STR1
0
0
STR0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Count Start 1
Selects whether to operate or halt the compare match
timer counter_1.
0: CMCNT_1 count operation halted
1: CMCNT_1 count operation
R/W Count Start 0
Selects whether to operate or halt the compare match
timer counter_0.
0: CMCNT_0 count operation halted
1: CMCNT_0 count operation
Rev.1.00 Sep. 18, 2008 Page 352 of 522
REJ09B0069-0100