SH7108 Datasheet, PDF (141/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Bus State Controller (BSC)
7.6.2 Wait State Control
The number of wait states inserted into external space access states can be controlled using the
WCR1 settings. The specified number of TW cycles are inserted as software cycles at the timing
shown in figure 7.4.
CK
Address
T1
TW
T2
Read
Data
Write
Data
Figure 7.4 Wait State Timing of External Space Access (Software Wait Only)
Rev.1.00 Sep. 18, 2008 Page 107 of 522
REJ09B0069-0100