SH7108 Datasheet, PDF (111/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Initial
Bit Bit Name Value R/W
4
IRQ3S 0
R/W
3 to 0 ⎯
All 0
R
Section 6 Interrupt Controller (INTC)
Description
IRQ3 Sense Select
Sets the IRQ3 interrupt request detection mode.
0: Interrupt request is detected at low level of IRQ3
input
1: Interrupt request is detected at edge of IRQ3 input
(edge direction is selected by ICR2)
Reserved
These bits are always read as 0. The write value should
always be 0.
6.3.2 Interrupt Control Register 2 (ICR2)
ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins IRQ0
to IRQ3. ICR2 is, however, valid only when IRQ interrupt request detection mode is set to the
edge detection mode by the sense select bits of IRQ0 to IRQ 3 in the interrupt control register 1
(ICR1). If the IRQ interrupt request detection mode has been set to low level detection mode, the
setting of ICR2 is ignored.
Initial
Bit Bit Name Value R/W
15 IRQ0ES1 0
R/W
14 IRQ0ES0 0
R/W
13 IRQ1ES1 0
R/W
12 IRQ1ES0 0
R/W
Description
These bits set the IRQ0 interrupt request edge detection
mode.
00: Interrupt request is detected at falling edge of IRQ0
input
01: Interrupt request is detected at rising edge of IRQ0
input
10: Interrupt request is detected at both falling and rising
edges of IRQ0 input
11: Setting prohibited
These bits set the IRQ1 interrupt request edge detection
mode.
00: Interrupt request is detected at falling edge of IRQ1
input
01: Interrupt request is detected at rising edge of IRQ1
input
10: Interrupt request is detected at both falling and rising
edges of IRQ1 input
11: Setting prohibited
Rev.1.00 Sep. 18, 2008 Page 77 of 522
REJ09B0069-0100