SH7108 Datasheet, PDF (400/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Motor Management Timer (MMT)
13.3.2 Timer Control Register (TCNR)
TCNR controls the enabling or disabling of interrupt requests, selects the enabling or disabling of
register access, selects counter operation or halting, and controls the enabling or disabling of
toggle output synchronized with the PWM period.
Initial
Bit Bit Name Value
7
TTGE
0
6
CST
0
5
RPRO
0
4 to 2 ⎯
All 0
1
TGIEN 0
0
TGIEM 0
R/W Description
R/W A/D Conversion Start Request Enable
Enables or disables the generation of A/D conversion
start requests when the TGFN or TGFM bit in the timer
status register (TSR) is set.
0: Disables the request
1: Enables the request
R/W Timer Counter Start
Selects operation or halting of the timer counter
(TCNT) and timer dead time counter (TDCNT).
0: TCNT and TDCNT operation is halted
1: TCNT and TDCNT perform count operations
R/W Register Protects
Enables or disables the reading of registers other than
TSR, and enables or disables the writing to registers
other than TBRU to TBRW, TPBR, and TSR. Writes to
TCNR itself are also disabled. Note that reset input is
necessary in order to write to these registers again.
0: Register access enabled
1: Register access disabled
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W TGR Interrupt Enable N
Enables or disables interrupt requests by the TGFN bit
when the TGFN bit is set to 1 in TSR.
0: Interrupt requests by TGFN bit disabled
1: Interrupt requests by TGFN bit enabled
R/W TGR Interrupt Enable M
Enables or disables interrupt requests by the TGFM bit
when the TGFM bit is set to 1 in TSR.
0: Interrupt requests by TGFM bit disabled
1: Interrupt requests by TGFM bit enabled
Rev.1.00 Sep. 18, 2008 Page 366 of 522
REJ09B0069-0100