SH7108 Datasheet, PDF (264/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this
point, TSR’s overflow flag TCFV bit is not set.
Figure 8.81 shows a TCFV bit operation example in reset sync PWM mode with a set value for
cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without
synchronous setting for the counter clear source.
TGRA_3
(H'FFFF)
Counter cleared by compare match 3A
TCNT_3 = TCNT_4
H'0000
TCFV_3
TCFV_4
Not set
Not set
Figure 8.81 Reset Sync PWM Mode Overflow Flag
8.7.16 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 8.82 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
Rev.1.00 Sep. 18, 2008 Page 230 of 522
REJ09B0069-0100