SH7108 Datasheet, PDF (203/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
Example of Cascaded Operation Setting Procedure: Figure 8.18 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
Start count
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
TCR to B'1111 to select TCNT_2 overflow/
underflow counting.
[2] Set the CST bit in TSTR for the upper and
lower channel to 1 to start the count
operation.
<Cascaded operation>
Figure 8.18 Cascaded Operation Setting Procedure
Examples of Cascaded Operation: Figure 8.19 illustrates the operation when TCNT_2
overflow/underflow counting has been set for TCNT_1 and phase counting mode has been
designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
TCNT_2
FFFD FFFE FFFF 0000 0001
0002
0001 0000 FFFF
TCNT_1
0000
0001
0000
Figure 8.19 Example of Cascaded Operation (2)
8.4.5 PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected
as 0, 1, or toggle output in response to a compare match of each TGR.
TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty
cycle.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
Rev.1.00 Sep. 18, 2008 Page 169 of 522
REJ09B0069-0100