SH7108 Datasheet, PDF (125/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Interrupt Controller (INTC)
Interrupt acceptance
1
3
5 + m1 + m2 + m3
3
m1 m2 1 m3 1
Instruction (instruction
replaced by interrupt
exception processing)
Overrun fetch
Interrupt service routine
start instruction
F DE E MMEME E
F
FDE
F: Instruction fetch (instruction fetched from memory where program is stored).
D: Instruction decoding (fetched instruction is decoded).
E: Instruction execution (data operation and address calculation is performed according to the results
of decoding).
M: Memory access (data in memory is accessed).
Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt Is Accepted
Rev.1.00 Sep. 18, 2008 Page 91 of 522
REJ09B0069-0100