SH7108 Datasheet, PDF (325/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 Serial Communication Interface (SCI)
Initial
Bit Bit Name Value R/W
Description
4
FER
0
R/(W)* Framing Error
[Setting condition]
• When the stop bit is 0
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
The FER flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
3
PER
0
R/(W)* Parity Error
[Setting condition]
• When a parity error is detected during reception
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
2
TEND
1
R
Transmit End
[Setting conditions]
• Power-on reset or software standby mode
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-
byte serial transmit character
[Clearing condition]
• When 0 is written to TDRE after reading TDRE = 1
1
MPB
0
R
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0, its previous state
is retained.
0
MPBT
0
R/W Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit value to be added to
the transmit data.
Note: * Only 0 can be written for flag clearing.
Rev.1.00 Sep. 18, 2008 Page 291 of 522
REJ09B0069-0100