SH7108 Datasheet, PDF (61/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Instruction Formats
nm format
15
0
xxxx nnnn mmmm xxxx
md format
15
0
xxxx xxxx mmmm dddd
nd4 format
15
xxxx xxxx
0
nnnn dddd
nmd format
15
0
xxxx nnnn mmmm dddd
Source
Operand
mmmm: Direct
register
mmmm: Direct
register
mmmm: Indirect
post-increment
register (multiply-
and-accumulate)
nnnn*: Indirect
post-increment
register (multiply-
and-accumulate)
mmmm: Indirect
post-increment
register
mmmm: Direct
register
mmmm: Direct
register
mmmmdddd:
Indirect register
with displacement
Destination
Operand
nnnn: Direct
register
nnnn: Indirect
register
MACH, MACL
Example
ADD Rm,Rn
MOV.L Rm,@Rn
MAC.W
@Rm+,@Rn+
nnnn: Direct
register
MOV.L @Rm+,Rn
nnnn: Indirect pre-
decrement
register
nnnn: Indirect
indexed register
R0 (Direct
register)
MOV.L Rm,@-Rn
MOV.L
Rm,@(R0,Rn)
MOV.B
@(disp,Rn),R0
R0 (Direct register) nnnndddd:
Indirect register
with displacement
MOV.B
R0,@(disp,Rn)
mmmm: Direct
register
mmmmdddd:
Indirect register
with displacement
nnnndddd: Indirect
register with
displacement
nnnn: Direct
register
MOV.L
Rm,@(disp,Rn)
MOV.L
@(disp,Rm),Rn
Rev.1.00 Sep. 18, 2008 Page 27 of 522
REJ09B0069-0100