SH7108 Datasheet, PDF (368/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 A/D Converter
11.3.2 A/D Control/Status Registers_0 to 2 (ADCSR_0 to ADCSR_2)
ADCSR for each module controls A/D conversion operations.
Bit Bit Name Initial Value R/W Description
7
ADF
0
R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all specified
channels in scan mode
[Clearing condition]
• When 0 is written after reading ADF = 1
6
ADIE
0
R/W A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when this bit is set to 1.
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCRs) to 0.
5
ADM1
0
4
ADM0
0
R/W A/D Mode 1 and 0
R/W Select the A/D conversion mode.
00: Single mode
01: 4-channel scan mode
10: 8-channel scan mode
11: Setting prohibited
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCRs) to 0.
For A/D2, the ADM1 bit must be cleared to 0.
3
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
2
CH2
0
1
CH1
0
R/W Channel Select 2 to 0
R/W Select analog input channels. See table 11.2.
0
CH0
0
R/W When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCRs) to 0.
Note: * Only 0 can be written to clear the flag.
Rev.1.00 Sep. 18, 2008 Page 334 of 522
REJ09B0069-0100