SH7108 Datasheet, PDF (110/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Interrupt Controller (INTC)
6.3.1 Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that sets the input signal detection mode of the external interrupt input
pins NMI and IRQ0 to IRQ3 and indicates the input signal level at the NMI pin.
Initial
Bit Bit Name Value R/W Description
15
NMIL
1/0
R
NMI Input Level
Sets the level of the signal input to the NMI pin. This bit
can be read to determine the NMI pin level. This bit
cannot be modified.
0: NMI input level is low
1: NMI input level is high
14 to 9 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
NMIE
0
R/W NMI Edge Select
0: Interrupt request is detected at falling edge of NMI
input
1: Interrupt request is detected at rising edge of NMI
input
7
IRQ0S
0
R/W IRQ0 Sense Select
Sets the IRQ0 interrupt request detection mode.
0: Interrupt request is detected at low level of IRQ0
input
1: Interrupt request is detected at edge of IRQ0 input
(edge direction is selected by ICR2)
6
IRQ1S
0
R/W IRQ1 Sense Select
Sets the IRQ1 interrupt request detection mode.
0: Interrupt request is detected at low level of IRQ1
input
1: Interrupt request is detected at edge of IRQ1 input
(edge direction is selected by ICR2)
5
IRQ2S
0
R/W IRQ2 Sense Select
Sets the IRQ2 interrupt request detection mode.
0: Interrupt request is detected at low level of IRQ2
input
1: Interrupt request is detected at edge of IRQ2 input
(edge direction is selected by ICR2)
Rev.1.00 Sep. 18, 2008 Page 76 of 522
REJ09B0069-0100