SH7108 Datasheet, PDF (145/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Bus State Controller (BSC)
7.8 Bus Arbitration
This LSI has a bus arbitration function that, when a bus release request is received from an
external device, releases the bus to that device. It also has an internal bus master, the CPU. The
priority for arbitrate the bus mastership between these bus masters is:
Bus request from external device > CPU
A bus request by an external device should be input to the BREQ pin. When the BREQ pin is
asserted, this LSI releases the bus immediately after the bus cycle being executed is completed.
The signal indicating that the bus has been released is output from the BACK pin.
However, the bus is not released between the read and write cycles during TAS instruction
execution. Bus arbitration is not executed between multiple bus cycles that occur due to the data
bus width smaller than access size, for instance, bus cycles in which 8-bit memory is accessed by a
longword.
The bus may be returned when this LSI is releasing the bus. That is, when interrupt request occurs
to be processed. This LSI incorporates the IRQOUT pin for the bus request signal. When the bus
must be returned to this LSI, the IRQOUT signal can be asserted. The device that is asserting an
external bus-release request negates the BREQ signal to release the bus when the IRQOUT signal
is asserted. As a result, the bus is returned to and processed by this LSI. The asserting condition of
the IRQOUT pin is that an interrupt source occurs and the interrupt request level is higher than
that of interrupt mask bits I3 to I0 in the status register (SR).
Figure 7.8 shows the bus mastership release procedure.
Rev.1.00 Sep. 18, 2008 Page 111 of 522
REJ09B0069-0100