SH7108 Datasheet, PDF (388/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 12 Compare Match Timer (CMT)
12.2.3 Compare Match Timer Counters_0 and 1 (CMCNT_0, CMCNT_1)
CMCNT is a 16-bit register used as an up-counter for generating interrupt requests. CMCNT is
initialized to H'0000.
12.2.4 Compare Match Timer Constant Registers_0 and 1 (CMCOR_0, CMCOR_1)
CMCOR is a 16-bit register that sets the period for compare match with CMCNT. CMCOR is
initialized to H'FFFF.
12.3 Operation
12.3.1 Cyclic Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT
counter value matches that of the compare match constant register (CMCOR), the CMCNT
counter is cleared to H'0000 and the CMF flag in CMCSR is set to 1. If the CMIE bit in CMCSR
is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins
counting up again from H'0000.
Figure 12.2 shows the compare match counter operation.
CMCNT value
CMCOR
Counter cleared by CMCOR
compare match
H'0000
Time
Figure 12.2 Counter Operation
Rev.1.00 Sep. 18, 2008 Page 354 of 522
REJ09B0069-0100