SH7108 Datasheet, PDF (410/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Motor Management Timer (MMT)
TDCNT1 starts counting at the falling edge of CMOUB. DTGUB outputs 0 if TDCNT1 is
counting, and 1 otherwise.
(c) Output Generation Waveform
Output generation waveform U phase A (OGUA) is generated by ANDing CMOUA and DTGUB,
and output generation waveform U phase B (OGUB) is generated by ANDing CMOUB and
DTGUA.
(d) PWM Waveform
The PWM waveform is generated by converting the output generation waveform to the output
level set in bits OLSN and OLSP in the timer mode register (TMDR).
Figure 13.5 shows an example of PWM waveform generation (operating mode 3, OLSN = 1,
OLSP = 1).
TPDR
When writing to free
operation address
2Td
Compare output
waveform
Dead time generation
waveform
Output generation
waveform
PWM waveform
Figure 13.5 Example of PWM Waveform Generation
(10) 0% to 100% Duty Cycle Output
In the operating modes, PWM waveforms with any duty cycle from 0% to 100% can be output.
The output PWM duty cycle is set using the buffer registers (TBRU to TBRW).
100% duty cycle output is performed when the buffer register (TBRU to TBRW) value is set to
H'0000. The waveform in this case has positive phase in the 100% on state. 0% duty cycle output
Rev.1.00 Sep. 18, 2008 Page 376 of 522
REJ09B0069-0100