SH7108 Datasheet, PDF (503/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 19 List of Registers
Register Name
Timer control/status register
Timer counter
Timer counter
Reset control/status register
Reset control/status register
Standby control register
Abbre-
viation
TCSR
TCNT*¹
TCNT*²
RSTCSR*¹
RSTCSR*²
SBYCR
—
System control register
—
SYSCR
—
—
Module standby control register 1 MSTCR1
Module standby control register 2 MSTCR2
Bus control register 1
BCR1
Bus control register 2
BCR2
Wait control register 1
WCR1
—
—
—
—
—
—
A/D trigger select register
—
ADTSR
—
Timer mode register
—
Timer control register
—
Timer status register
—
Timer counter
Timer period data register
Timer period buffer register
Timer dead time data register
MMT_TMDR
—
TCNR
—
MMT_TSR
—
MMT_TCNT
TPDR
TPBR
MMT_TDDR
Bits Address
Module
8 H'FFFF8610
8 H'FFFF8610
8 H'FFFF8611
8 H'FFFF8612
8 H'FFFF8613
WDT
*1: Write
cycle
*2: Read
cycle
8 H'FFFF8614
Power-
down
modes
— H'FFFF8615 to —
H'FFFF8617
8 H'FFFF8618
Power-
down
modes
— H'FFFF8619 to
H'FFFF861B
16 H'FFFF861C
16 H'FFFF861E
16 H'FFFF8620 BSC
16 H'FFFF8622
16 H'FFFF8624
— H'FFFF8626
— H'FFFF8628 to —
H'FFFF864F
— H'FFFF8650 to —
H'FFFF87F3
8 H'FFFF87F4 A/D
— H'FFFF87F5 to
H'FFFF89FF
8 H'FFFF8A00 MMT
— H'FFFF8A01
8 H'FFFF8A02
— H'FFFF8A03
8 H'FFFF8A04
— H'FFFF8A05
16 H'FFFF8A06
16 H'FFFF8A08
16 H'FFFF8A0A
16 H'FFFF8A0C
Access Access
Size States
8*²/16*¹
16
8
In φ cycles
B: 3
W: 3
16
8
8
In φ cycles
B: 3
—
—
8
In Pφ cycles
B: 3
W: 3
—
L: 6
8, 16, 32
8, 16
8, 16, 32
8, 16
8, 16
—
In φ cycles
B: 3
W: 3
L: 6
—
—
—
—
8
In Pφ cycles
—
B: 3
8
—
8
—
8
—
16
16, 32
16
16
In Pφ cycles
B: 2
W: 2
L: 4
Rev.1.00 Sep. 18, 2008 Page 469 of 522
REJ09B0069-0100