SH7108 Datasheet, PDF (37/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1.2 Internal Block Diagram
Section 1 Overview
RES
WDTOVF
MD3
MD2
MD1
MD0
NMI
EXTAL
XTAL
PLLVCL
PLLCAP
PLLVss
Vcc
VCL
VCL
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
AVcc
AVcc
AVss
AVss
Masked ROM
256 kbytes/128 kbytes/
64 kbytes/32 kbytes
RAM
8 kbytes/4 kbytes/
2 kbytes
CPU
Interrupt controller
Bus state controller
Serial communication
interface (x 2 channels)
Multifunction timer
pulse unit
Compare match timer
(x 2 channels)
A/D
Watchdog
converter timer
Motor management
timer (x 1 channel)
: Peripheral address bus (12 bits)
: Peripheral data bus (16 bits)
: Internal address bus (32 bits)
: Internal upper data bus (16 bits)
: Internal lower data bus (16 bits)
Figure 1.1 Internal Block Diagram of SH7108/SH7106/SH7104/SH7101
Rev.1.00 Sep. 18, 2008 Page 3 of 522
REJ09B0069-0100